Digital Logic @ 45 Days

Digital Logic Bachelor of Engineering(DL)(BE) videos According to syllabus of Institute of Engineering(IoE), Tribhuwan University (TU)

Advanced 5 (6 Reviews ) 255 Students enrolled
Last updated Wed, 09-Oct-2024 Nepali
What will I learn?
  • Outcomes

Curriculum for this course
167 Lessons 18h 14m
0. How to Purchase Course from MeroSchool
1 Lessons
  • 0. How to Purchase Course from MeroSchool.mp4 00:03:30
  • 1. Syllabus and marks distribution.mp4 00:02:29
  • 1. Introduction.mp4 00:04:00
  • 2. Digital Computer.mp4 00:05:49
  • 3. BCD code.mp4 00:08:13
  • 1. Basic Gate.mp4 00:03:24
  • 2. Universal Gate.mp4 00:02:28
  • 3. X-OR and X-NOR gates.mp4 00:03:05
  • 4. NAND as universal gate.mp4 00:08:12
  • 5. NOR as universal gate.mp4 00:05:54
  • 6. AND or INVERT gate.mp4 00:07:34
  • 1. Introduction.mp4 00:10:23
  • 2. minterm maxterm.mp4 00:11:45
  • 3. K-MAP theory.mp4 00:09:21
  • 4. K-MAP Example 1.mp4 00:11:39
  • 5. K-MAP Example 2.mp4 00:19:06
  • 6. K-MAP Example 3.mp4 00:08:07
  • 7. Hazard and hazard cover.mp4 00:11:09
  • 1. Combinational Circuit.mp4 00:14:19
  • 2. MUX DESIGN (Part 1).mp4 00:06:30
  • 3. MUX Design Part 2.mp4 00:06:49
  • 4. MUX DESIGN Part 3.mp4 00:07:37
  • 5. Demultiplexer.mp4 00:10:39
  • 6. Decoder.mp4 00:12:11
  • 7. BCD to Decimal Decoder.mp4 00:05:07
  • 8. Decoder Construction.mp4 00:04:02
  • 9. Seven segment (part 1).mp4 00:07:10
  • 10. Seven Segment(part 2).mp4 00:16:19
  • 11. Priority encoder.mp4 00:09:44
  • 12. Octal to binary encoder.mp4 00:04:34
  • 13. parity generator and checkers.mp4 00:06:56
  • 14. Magnitude comparator.mp4 00:03:10
  • 15. 2bit magnitute comparator.mp4 00:12:00
  • 16. ROM.mp4 00:12:37
  • 17. PLA.mp4 00:05:35
  • 18. PAL.mp4 00:06:14
  • 1. binary addtion.mp4 00:06:33
  • 2. 2'complement.mp4 00:07:51
  • 3. Half Adder and Full Adder.mp4 00:09:09
  • 4. Adder subtractor.mp4 00:09:08
  • 5. ALU,BInary multiplication and division.mp4 00:06:54
  • 6. Fast adder.mp4 00:15:38
  • 1. SR flipflop.mp4 00:12:14
  • 2. D flipflop.mp4 00:04:22
  • 3. jk flipflop.mp4 00:07:58
  • 4. race around.mp4 00:01:57
  • 5. master-slave jk.mp4 00:03:20
  • 6. T flipflop.mp4 00:04:13
  • 7. SR-JK conversion.mp4 00:04:24
  • 8. SR-T conversion.mp4 00:03:08
  • 9. contact bounce circuit.mp4 00:05:54
  • 10. Output Waveform.mp4 00:02:26
  • 11. Concept video.mp4 00:10:56
  • 1. Register Introduction.mp4 00:03:19
  • 2. SISO register.mp4 00:08:24
  • 3. SIPO register.mp4 00:07:09
  • 4.PISO register.mp4 00:10:29
  • 5. PIPO register.mp4 00:03:13
  • 6. Ring Countere.mp4 00:07:09
  • 7. Johnson counter.mp4 00:08:36
  • 1. 3-bit ripple up counter.mp4 00:08:30
  • 2. 3-bit down counter.mp4 00:03:33
  • 3. 3-bit ripple up-down counter.mp4 00:06:50
  • 4. Decoding gates.mp4 00:05:17
  • 5. 3-bit synchronous up counter.mp4 00:13:49
  • 6. 3-bit down synchronous counter.mp4 00:06:26
  • 7. 3-bit ripple up-down counter.mp4 00:06:50
  • 8. Decade counter.mp4 00:05:19
  • 9. Counter design as a synthesis problem(synchronous counter).mp4 00:08:16
  • 10. Digital clock.mp4 00:05:20
  • 11. Presettable counter.mp4 00:10:05
  • 1. Sequential machine introduction.mp4 00:14:25
  • 2. State diagram tips.mp4 00:07:09
  • 3. Moore model design.mp4 00:15:29
  • 4. Mealy model example 1.mp4 00:10:49
  • 5. Melay model example no 2.mp4 00:13:13
  • 6. State reduction technique.mp4 00:04:16
  • 7. analysis of asynchronous circuit.mp4 00:06:27
  • 8. problems with asynchronous ckt.mp4 00:08:40
  • 1. Switching circuit.mp4 00:06:26
  • 2. Characteristic of TTL.mp4 00:02:05
  • 3. TTL as NAND gate.mp4 00:07:14
  • 4. TTL parameter.mp4 00:02:57
  • 5. TTL ovierview (TTL as NOT gate).mp4 00:05:45
  • 6. TTL as NOR gate.mp4 00:07:41
  • 7. TTL as AND and OR.mp4 00:10:58
  • 8. Open collector Gate.mp4 00:02:37
  • 9. Tristate TTL logic.mp4 00:05:15
  • 10. External drive for TTL loads.mp4 00:04:27
  • 11. TTL drive external load.mp4 00:01:57
  • 12. CMOS NOR.mp4 00:05:52
  • 13. CMOS as NAND gate.mp4 00:03:45
  • 14. TTL to CMOS interface.mp4 00:02:25
  • 15. CMOS to TTL interface.mp4 00:02:30
  • 1. Multiplexed display.mp4 00:02:37
  • 2. Frequency counter.mp4 00:03:05
  • 3. Time measurement.mp4 00:03:51
  • 2073 Chaitra|Q. 1a.mp4 00:01:06
  • 2073 Chaitra|Q. 1b.mp4 00:15:11
  • 2073 Chaitra|Q. 2.mp4 00:07:11
  • 2073 Chaitra|Q. 3.mp4 00:03:59
  • 2073 Chaitra|Q. 4a.mp4 00:03:04
  • 2073 Chaitra|Q. 4b.mp4 00:02:45
  • 2073 Chaitra|Q. 5.mp4 00:05:53
  • 2073 Chaitra|Q. 6.mp4 00:15:19
  • 2073 Chaitra|Q. 7.mp4 00:03:15
  • 2073 Chaitra|Q. 8.mp4 00:05:56
  • 2073 Chaitra|Q. 9.mp4 00:12:12
  • 2073 Chaitra|Q. 10.mp4 00:04:26
  • 2073 Chaitra|Q. 11.mp4 00:03:03
  • 2073 Chaitra|Q. 12.mp4 00:03:00
  • 2074 Ashwin|Q. 1a.mp4 00:00:54
  • 2074 Ashwin|Q. 1b.mp4 00:04:26
  • 2074 Ashwin|Q. 2.mp4 00:06:22
  • 2074 Ashwin|Q. 3.mp4 00:03:27
  • 2074 Ashwin|Q. 4a.mp4 00:00:59
  • 2074 Ashwin|Q. 4b.mp4 00:04:54
  • 2074 Ashwin|Q. 5.mp4 00:10:09
  • 2074 Ashwin|Q. 6.mp4 00:00:46
  • 2074 Ashwin|Q. 7.mp4 00:09:40
  • 2074 Ashwin|Q. 8.mp4 00:11:11
  • 2074 Ashwin|Q. 9.mp4 00:01:14
  • 2074 Ashwin|Q. 10.mp4 00:05:18
  • 2074 Ashwin|Q. 11.mp4 00:06:26
  • 2074 Chaitra|Q. 1a.mp4 00:02:52
  • 2074 Chaitra|Q. 1b.mp4 00:03:55
  • 2074 Chaitra|Q. 2a.mp4 00:02:27
  • 2074 Chaitra|Q. 2b.mp4 00:01:44
  • 2074 Chaitra|Q. 3a.mp4 00:07:01
  • 2074 Chaitra|Q. 3b.mp4 00:01:36
  • 2074 Chaitra|Q. 4.mp4 00:08:21
  • 2074 Chaitra|Q. 5a.mp4 00:14:22
  • 2074 Chaitra|Q. 5b.mp4 00:02:09
  • 2074 Chaitra|Q. 6a.mp4 00:06:22
  • 2074 Chaitra|Q. 6b.mp4 00:00:44
  • 2074 Chaitra|Q. 7.mp4 00:11:10
  • 2074 Chaitra|Q. 8.mp4 00:13:18
  • 2074 Chaitra|Q. 9.mp4 00:00:47
  • 2074 Chaitra|Q. 10.mp4 00:00:42
  • 2074 Chaitra|Q. 11.mp4 00:05:30
  • 2074 Chaitra|Q. 12.mp4 00:03:00
  • 2075 Ashwin|Q. 1.mp4 00:05:18
  • 2075 Ashwin|Q. 2.mp4 00:01:55
  • 2075 Ashwin|Q. 3.mp4 00:05:04
  • 2075 Ashwin|Q. 4.mp4 00:08:45
  • 2075 Ashwin|Q. 5.mp4 00:06:37
  • 2075 Ashwin|Q. 6.mp4 00:04:58
  • 2075 Ashwin|Q. 7.mp4 00:03:58
  • 2075 Ashwin|Q. 8.mp4 00:02:19
  • 2075 Ashwin|Q. 9.mp4 00:03:36
  • 2075 Ashwin|Q. 10.mp4 00:09:33
  • 2075 Ashwin|Q. 11.mp4 00:00:41
  • 2075 Ashwin|Q. 12.mp4 00:09:07
  • 2075 Ashwin|Q. 13.mp4 00:02:15
  • 2075 Ashwin|Q. 14.mp4 00:03:38
  • 2076 Chaitra|Q. 1&2.mp4 00:11:27
  • 2076 Chaitra|Q. 3.mp4 00:06:51
  • 2076 Chaitra|Q. 4.mp4 00:03:57
  • 2076 Chaitra|Q. 5.mp4 00:09:43
  • 2076 Chaitra|Q. 6.mp4 00:06:55
  • 2076 Chaitra|Q. 7.mp4 00:05:20
  • 2076 Chaitra|Q. 8.mp4 00:04:10
  • 2076 Chaitra|Q. 9.mp4 00:06:55
  • 2076 Chaitra|Q. 10.mp4 00:12:32
  • 2076 Chaitra|Q. 11.mp4 00:05:04
  • 2076 Chaitra|Q. 12.mp4 00:03:01
  • 2076 Chaitra|Q. 13.mp4 00:18:32
Requirements
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Description

The videos herein are strictly based on syllabus of Institute of Engineering Tribhuwan University, Nepal promoting "e-Learning in Nepal" and are made with intention to provide guidance to the "Bachelor in Engineering(BE) appearing students", for securing good results. The course tries to cover all the basics of Digital Logic. This course also includes the frequently asked questions with solutions which will be highly benefitted to the students. We strongly believe that, viewers will be benefited from these videos and the thirst of curiosity of viewers will be quenched! Feedbacks and suggestion to improve are always welcome and highly appreciated!

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Rs 999 Rs 1499
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Includes:
  • 18+ Hours On demand videos
  • 167 Lessons
  • 45 Days Subscription
  • Access On Mobile And Web

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