Digital Logic

Digital Logic Bachelor of Engineering(BE) videos According to syllabus of Institute of Engineering(IoE), Tribhuwan University (TU)

Advanced 5 (4 Reviews ) 27 Students enrolled
Created by Mero School Last updated Thu, 25-Nov-2021 Nepali
What will I learn?
  • Outcomes

Curriculum for this course
164 Lessons 17:47:16 H:M:S
1. Mark Distribution
1 Lessons 00:02:29 Hours
  • Syllabus and marks distribution 00:02:29 Free
  • 1. Introduction 00:04:00 Free
  • 2. Digital Computer 00:05:49 Free
  • 3. BCD code 00:08:13
  • 1. Basic Gate 00:03:24
  • 2. Universal Gate 00:02:28
  • 3. X-OR and X-NOR gates 00:03:05
  • 4. NAND as universal gate 00:02:24
  • 5. NOR as universal gate 00:05:54
  • 6. AND or INVERT gate 00:07:34
  • 1. Introduction 00:10:23
  • 2. minterm maxterm 00:11:45
  • 3. K-MAP theory 00:09:21
  • 4. K-MAP Example 1 00:11:39
  • 5. K-MAP Example 2 00:19:06
  • 6. K-MAP Example 3 00:08:07
  • 7. Hazard and hazard cover 00:11:09
  • 1. Combinational Circuit 00:14:20
  • 2. MUX DESIGN (Part 1) 00:06:30
  • 3. MUX Design Part 2 00:06:49
  • 4. MUX DESIGN Part 3 00:07:37
  • 5. Demultiplexer 00:10:39
  • 6. Decoder 00:12:11
  • 7. BCD to Decimal Decoder 00:05:14
  • 8. Decoder Construction 00:04:02
  • 9. Seven segment (part 1) 00:07:10
  • 10. Seven Segment(part 2) 00:17:52
  • 11. Priority encoder 00:09:44
  • 12. Octal to binary encoder 00:04:34
  • 13. parity generetor and checkers 00:06:56
  • 14. Magnitude comparator 00:03:10
  • 15. 2bit magnitute comparator 00:12:00
  • 16. ROM 00:12:37
  • 17. PLA 00:05:35
  • 18. PAL 00:06:14
  • 1. binary addtion 00:06:33
  • 2. 2'complement 00:07:51
  • 3. Half Adder and Full Adder 00:09:09
  • 4. Adder subtractor 00:09:08
  • 5. ALU,BInary multiplication and division 00:06:54
  • 6. Fast adder 00:15:38
  • 1. SR flipflop 00:12:14
  • 2. D flipflop 00:04:22
  • 3. jk flipflop 00:07:58
  • 4. race around 00:01:57
  • 5. master-slave jk 00:03:20
  • 6. T flipflop 00:04:13
  • 7. SR-JK conversion 00:04:24
  • 8. SR-T conversion 00:03:08
  • 9. contact bounce circuit 00:05:54
  • 10. output waveform 00:02:26
  • 1. Register Introduction 00:03:19
  • 2. SISO register 00:08:24
  • 3. SIPO register 00:07:10
  • 4.PISO register 00:10:29
  • 5. PIPO register 00:03:13
  • 6. Ring Countere 00:07:09
  • 7. Johnson counter 00:08:36
  • 1. 3-bit ripple up counter 00:08:30
  • 2. 3-bit down counter 00:03:33
  • 3. 3-bit ripple up-down counter 00:06:50
  • 4. Decoding gates 00:05:17
  • 5. 3-bit synchronous up counter 00:13:49
  • 6. 3-bit down synchronous counter 00:06:26
  • 7. 3-bit ripple up-down counter 00:06:50
  • 8. Decade counter 00:05:19
  • 9. Counter design as a synthesis problem(synchronous counter) 00:08:16
  • 10. Digital clock 00:05:20
  • 1. Sequential machine introduction 00:14:25
  • 2. State diagram tips 00:07:10
  • 3. Moore model design 00:15:29
  • 4. Mealy model example 1 00:10:49
  • 5. Melay model example no 2 00:13:13
  • 6. State reduction technique 00:04:16
  • 7. analysis of asynchronous circuit 00:06:27
  • 8. problems with asynchronous ckt 00:08:40
  • 1. Switching circuit 00:06:26
  • 2. Characteristic of TTL 00:02:05
  • 3. TTL as Nand gate 00:07:14
  • 4. TTl parameter 00:02:57
  • 5. TTL ovierview (TTL as not gate) 00:05:45
  • 6. TTL as nor gate 00:07:41
  • 7. TTL as AND and OR 00:10:58
  • 8. Open collector Gate 00:02:37
  • 9. Tristate TTL logic 00:05:15
  • 10. External drive for ttl loads 00:04:27
  • 11. TTL drive external load 00:01:57
  • 12. CMOS NOR 00:05:52
  • 13. CMOS as NAND gate 00:03:45
  • 14. TTL to CMOS interface 00:02:25
  • 15. COMOS to TTL interface 00:02:30
  • 1. Multiplexed display 00:02:37
  • 2. Frequency counter 00:03:05
  • 3. Time measurement 00:03:51
  • 1. 2073 Chaitra
    • Q. 1a 00:01:06
    • Q. 1b 00:15:11
    • Q. 2 00:07:11
    • Q. 3 00:03:59
    • Q. 4a 00:03:04
    • Q. 4b 00:02:45
    • Q. 5 00:05:53
    • Q. 6 00:15:19
    • Q. 7 00:03:15
    • Q. 8 00:05:56
    • Q. 9 00:12:12
    • Q. 10 00:04:26
    • Q. 11 00:03:03
    • Q. 12 00:03:00
    2. 2074 Ashwin
    • Q. 1a 00:00:54
    • Q. 1b 00:04:26
    • Q. 2 00:06:22
    • Q. 3 00:03:27
    • Q. 4a 00:00:59
    • Q. 4b 00:04:54
    • Q. 5 00:10:09
    • Q. 6 00:00:46
    • Q. 7 00:09:40
    • Q. 8 00:11:11
    • Q. 9 00:01:14
    • Q. 10 00:05:18
    • Q. 11 00:06:26
    3. 2074 Chaitra
    • Q. 1a 00:02:52
    • Q. 1b 00:03:55
    • Q. 2a 00:02:27
    • Q. 2b 00:01:44
    • Q. 3a 00:07:01
    • Q. 3b 00:01:36
    • Q. 4 00:08:21
    • Q. 5a 00:14:22
    • Q. 5b 00:02:10
    • Q. 6a 00:06:22
    • Q. 6b 00:00:44
    • Q. 7 00:11:10
    • Q. 8 00:13:18
    • Q. 9 00:00:48
    • Q. 10 00:00:42
    • Q. 11 00:05:30
    • Q. 12 00:03:00
    4. 2075 Ashwin
    • Q. 1 00:05:18
    • Q. 2 00:01:55
    • Q. 3 00:05:04
    • Q. 4 00:08:45
    • Q. 5 00:06:37
    • Q. 6 00:04:58
    • Q. 7 00:03:58
    • Q. 8 00:02:19
    • Q. 9 00:03:37
    • Q. 10 00:09:33
    • Q. 11 00:00:42
    • Q. 12 00:09:07
    • Q. 13 00:02:15
    • Q. 14 00:03:38
    5. 2076 Chaitra
    • Q. 1&2 00:11:27
    • Q. 3 00:06:51
    • Q. 4 00:03:57
    • Q. 5 00:09:43
    • Q. 6 00:06:55
    • Q. 7 00:05:20
    • Q. 8 00:04:10
    • Q. 9 00:06:55
    • Q. 10 00:12:32
    • Q. 11 00:05:04
    • Q. 12 00:03:01
    • Q. 13 00:18:32
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    Description

    The videos herein are strictly based on syllabus of Institute of Engineering Tribhuwan University, Nepal promoting "e-Learning in Nepal" and are made with intention to provide guidance to the "Bachelor in Engineering(BE) appearing students", for securing good results. The course tries to cover all the basics of Digital Logic. This course also includes the frequently asked questions with solutions which will be highly benefitted to the students. We strongly believe that, viewers will be benefited from these videos and the thirst of curiosity of viewers will be quenched! Feedbacks and suggestion to improve are always welcome and highly appreciated!

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    Includes:
    • 17:47:16 On demand videos
    • 164 Lessons
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