Digital Logic

Digital Logic Bachelor of Engineering(DL)(BE) videos According to syllabus of Institute of Engineering(IoE), Tribhuwan University (TU)

Advanced 5 (5 Reviews ) 87 Students enrolled
Last updated Sun, 17-Jul-2022 Nepali
What will I learn?
• Outcomes

Curriculum for this course
166 Lessons 18h 0m
1. Mark Distribution
1 Lessons 2m
• Syllabus and marks distribution 2 Minutes Free
• 1. Introduction 4 Minutes Free
• 2. Digital Computer 5 Minutes Free
• 3. BCD code 8 Minutes Free
• 1. Basic Gate 3 Minutes
• 2. Universal Gate 2 Minutes
• 3. X-OR and X-NOR gates 3 Minutes
• 4. NAND as universal gate 8 Minutes
• 5. NOR as universal gate 5 Minutes
• 6. AND or INVERT gate 7 Minutes
• 1. Introduction 10 Minutes
• 2. Minterm maxterm 11 Minutes
• 3. K-MAP theory 9 Minutes
• 4. K-MAP Example 1 11 Minutes
• 5. K-MAP Example 2 19 Minutes
• 6. K-MAP Example 3 8 Minutes
• 7. Hazard and hazard cover 11 Minutes
• 1. Combinational Circuit 14 Minutes
• 2. MUX DESIGN (Part 1) 6 Minutes
• 3. MUX Design Part 2 6 Minutes
• 4. MUX DESIGN Part 3 7 Minutes
• 5. Demultiplexer 10 Minutes
• 6. Decoder 12 Minutes
• 7. BCD to Decimal Decoder 5 Minutes
• 8. Decoder Construction 4 Minutes
• 9. Seven segment (part 1) 7 Minutes
• 10. Seven Segment(part 2) 16 Minutes
• 11. Priority encoder 9 Minutes
• 12. Octal to binary encoder 4 Minutes
• 13. Parity generator and checkers 6 Minutes
• 14. Magnitude comparator 3 Minutes
• 15. 2bit magnitute comparator 12 Minutes
• 16. ROM 12 Minutes
• 17. PLA 5 Minutes
• 18. PAL 6 Minutes
• 1. binary addtion 6 Minutes
• 2. 2'complement 7 Minutes
• 4. Adder subtractor 9 Minutes
• 5. ALU,BInary multiplication and division 6 Minutes
• 6. Fast adder 15 Minutes
• 1. SR flipflop 12 Minutes
• 2. D flipflop 4 Minutes
• 3. jk flipflop 7 Minutes
• 4. race around 1 Minutes
• 5. master-slave jk 3 Minutes
• 6. T flipflop 4 Minutes
• 7. SR-JK conversion 4 Minutes
• 8. SR-T conversion 3 Minutes
• 9. contact bounce circuit 5 Minutes
• 10. Output Waveform 2 Minutes
• 11. Concept video 10 Minutes
• 1. Register Introduction 3 Minutes
• 2. SISO register 8 Minutes
• 3. SIPO register 7 Minutes
• 4.PISO register 10 Minutes
• 5. PIPO register 3 Minutes
• 6. Ring Countere 7 Minutes
• 7. Johnson counter 8 Minutes
• 1. 3-bit ripple up counter 8 Minutes
• 2. 3-bit down counter 3 Minutes
• 3. 3-bit ripple up-down counter 6 Minutes
• 4. Decoding gates 5 Minutes
• 5. 3-bit synchronous up counter 13 Minutes
• 6. 3-bit down synchronous counter 6 Minutes
• 7. 3-bit ripple up-down counter 6 Minutes
• 8. Decade counter 5 Minutes
• 9. Counter design as a synthesis problem(synchronous counter) 8 Minutes
• 10. Digital clock 5 Minutes
• 11. Presettable counter 10 Minutes
• 1. Sequential machine introduction 14 Minutes
• 2. State diagram tips 7 Minutes
• 3. Moore model design 15 Minutes
• 4. Mealy model example 1 10 Minutes
• 5. Melay model example no 2 13 Minutes
• 6. State reduction technique 4 Minutes
• 7. analysis of asynchronous circuit 6 Minutes
• 8. problems with asynchronous ckt 8 Minutes
• 1. Switching circuit 6 Minutes
• 2. Characteristic of TTL 2 Minutes
• 3. TTL as NAND gate 7 Minutes
• 4. TTL parameter 2 Minutes
• 5. TTL ovierview (TTL as NOT gate) 5 Minutes
• 6. TTL as NOR gate 7 Minutes
• 7. TTL as AND and OR 10 Minutes
• 8. Open collector Gate 2 Minutes
• 9. Tristate TTL logic 5 Minutes
• 10. External drive for TTL loads 4 Minutes
• 11. TTL drive external load 1 Minutes
• 12. CMOS NOR 5 Minutes
• 13. CMOS as NAND gate 3 Minutes
• 14. TTL to CMOS interface 2 Minutes
• 15. CMOS to TTL interface 2 Minutes
• 1. Multiplexed display 2 Minutes
• 2. Frequency counter 3 Minutes
• 3. Time measurement 3 Minutes
• 1. 2073 Chaitra
• Q. 1a 1 Minutes
• Q. 1b 15 Minutes
• Q. 2 7 Minutes
• Q. 3 3 Minutes
• Q. 4a 3 Minutes
• Q. 4b 2 Minutes
• Q. 5 5 Minutes
• Q. 6 15 Minutes
• Q. 7 3 Minutes
• Q. 8 5 Minutes
• Q. 9 12 Minutes
• Q. 10 4 Minutes
• Q. 11 3 Minutes
• Q. 12 3 Minutes
2. 2074 Chaitra
• Q. 1a 2 Minutes
• Q. 1b 3 Minutes
• Q. 2a 2 Minutes
• Q. 2b 1 Minutes
• Q. 3a 7 Minutes
• Q. 3b 1 Minutes
• Q. 4 8 Minutes
• Q. 5a 14 Minutes
• Q. 5b 2 Minutes
• Q. 6a 6 Minutes
• Q. 6b 0 Minutes
• Q. 7 11 Minutes
• Q. 8 13 Minutes
• Q. 9 0 Minutes
• Q. 10 0 Minutes
• Q. 11 5 Minutes
• Q. 12 3 Minutes
3. 2075 Ashwin
• Q. 1 5 Minutes
• Q. 2 1 Minutes
• Q. 3 5 Minutes
• Q. 4 8 Minutes
• Q. 5 6 Minutes
• Q. 6 4 Minutes
• Q. 7 3 Minutes
• Q. 8 2 Minutes
• Q. 9 3 Minutes
• Q. 10 9 Minutes
• Q. 11 0 Minutes
• Q. 12 9 Minutes
• Q. 13 2 Minutes
• Q. 14 3 Minutes
4. 2076 Chaitra
• Q. 1&2 11 Minutes
• Q. 3 6 Minutes
• Q. 4 3 Minutes
• Q. 5 9 Minutes
• Q. 6 6 Minutes
• Q. 7 5 Minutes
• Q. 8 4 Minutes
• Q. 9 6 Minutes
• Q. 10 12 Minutes
• Q. 11 5 Minutes
• Q. 12 3 Minutes
• Q. 13 18 Minutes
5. 2074 Ashwin
• Q. 1a 0 Minutes
• Q. 1b 4 Minutes
• Q. 2 6 Minutes
• Q. 3 3 Minutes
• Q. 4a 0 Minutes
• Q. 4b 4 Minutes
• Q. 5 10 Minutes
• Q. 6 0 Minutes
• Q. 7 9 Minutes
• Q. 8 11 Minutes
• Q. 9 1 Minutes
• Q. 10 5 Minutes
• Q. 11 6 Minutes
Requirements
• Requirements
Description

The videos herein are strictly based on syllabus of Institute of Engineering Tribhuwan University, Nepal promoting "e-Learning in Nepal" and are made with intention to provide guidance to the "Bachelor in Engineering(BE) appearing students", for securing good results. The course tries to cover all the basics of Digital Logic. This course also includes the frequently asked questions with solutions which will be highly benefitted to the students. We strongly believe that, viewers will be benefited from these videos and the thirst of curiosity of viewers will be quenched! Feedbacks and suggestion to improve are always welcome and highly appreciated!

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Includes:
• 18+ Hours On demand videos
• 166 Lessons
• 30 Days Subscription
• Access On Mobile And Web

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